Intel Claims Its 10nm Chips Will Be a 'Generation Ahead' of Samsung's

Intel Claims Its 10nm Chips Will Be a 'Generation Ahead' of Samsung's
  • New chips claimed to deliver 25 percent improved performance
  • The upcoming chips have been claimed to be power efficient as well
  • The new chips are based on third-generation FinFET technology

Bold claims often come back to haunt companies in tech industry but Intel seems to be confident about the performance of its upcoming Cannon Lake chips as the company has claimed that its 10nm chips will be "generation ahead" of other chips based on 10nm technology. Intel's upcoming chips make use of third-generation FinFET technology and company says that its 10nm process technology will be used to fabricate the full range of Intel products serving the client, server, and other market segments.

"Intel's 10 nm process delivers up to 25 percent better performance and 45 percent lower power than the previous 14nm technology," Intel said in its release, as pointed out by Engadget. The company also plans to introduce an enhanced version of the 10nm process, called 10+ and 10++, in future which boosts the performance an additional 15 percent while reducing power consumption by another 30 percent.

Intel says that the use of hyperscaling on its 10nm technology gets the "full value" of multi-patterning schemes, managing to fit in twice as many transistors into the same die size. Further, the chipmaker says that the hyperscaling helps it continue the benefits of Moore's Law economics by delivering transistors that are smaller and have lower cost-per-transistor than its competitors.

Considering that Samsung is building Qualcomm's Snapdragon 835 SoC as well as its own Exynos 8890 SoC based on a 10nm FinFET process, Intel seems to be indicating that its chips will be superior to those made by the South Korean company, and those being made by TSMC right now. Intel made these announcements on Wednesday, at its Technology and Manufacturing Day.

"The minimum gate pitch of Intel's 10nm process shrinks from 70nm to 54nm and the minimum metal pitch shrinks from 52 nm to 36 nm. These smaller dimensions enable a logic transistor density of 100.8 mega transistors per mm2, which is 2.7x higher than Intel's previous 14 nm technology and is expected to be approximately 2x higher than other industry 10 nm technologies," it said.


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